Transistor manufacturing method

专利摘要:
The present invention relates to a transistor manufacturing method, in order to prevent the deterioration of the characteristics of the device according to the size of the gate electrode formed by forming the gate electrode in the Y-shaped channel length can be reduced without increasing the cross-sectional area of the gate electrode. Therefore, an increase in the self-resistance value due to the decrease in the size of the gate electrode is prevented and the short channel effect and the hot electron effect are suppressed. In addition, according to the present invention, a gate electrode having a polyside structure can be easily formed, and since the oxide spacer is not formed on the sidewall of the gate electrode, a junction leakage current does not occur during operation of the device. Therefore, the reliability and yield of the device can be improved.
公开号:KR19980052498A
申请号:KR1019960071502
申请日:1996-12-24
公开日:1998-09-25
发明作者:김정태
申请人:김영환；현대전자산업 주식회사；
IPC主号:

专利说明:

Transistor manufacturing method
The present invention relates to a method for manufacturing a transistor, and more particularly, to a method for manufacturing a transistor of a semiconductor device having a lightly doped drain (LDD) structure.
In general, a transistor consists of a gate electrode, a source and a drain region. The gate electrode is made of a conductive material such as polysilicon and is electrically separated from the lower silicon substrate by a gate oxide film. The source and drain regions are formed on the silicon substrate at both sides of the gate electrode and include a junction region into which impurity ions are implanted.
Conventionally, in order to manufacture a transistor, first, a gate upper layer and a polysilicon layer are sequentially formed on a silicon substrate, and then the polysilicon layer and the gate oxide layer are sequentially patterned to form a gate electrode. A low concentration of impurity ions are implanted into the silicon substrate on both sides of the gate electrode to form an LDD region, and then insulating film spacers are formed on both sidewalls of the gate electrode. A high concentration of impurity ions are implanted into the exposed silicon substrate to form a junction region.
However, when using the conventional method as described above, the silicon substrate of the exposed portion is damaged during the dry etching process for forming the insulating film spacer. In the subsequent heat treatment, stress is generated due to the difference in thermal expansion coefficient between the polysilicon forming the gate electrode and the insulating film spacer, and the generated stress is applied to the silicon substrate. Therefore, such a phenomenon causes leakage current during operation of the device. In addition, during the implantation of the high concentration impurity ions, oxygen, which is bounced from the insulating layer spacer, is injected into the junction region, thereby acting as a factor that prevents subsequent defect removal.
As the semiconductor device is highly integrated, the size of the gate electrode is also reduced. Therefore, the operating speed of the device is reduced due to the increase in the self resistance of the gate electrode. Therefore, to prevent this, a gate electrode having a polycide (Polycide) structure is formed using tungsten or titanium silicide. In this case, however, the self-resistance value of the gate electrode and the junction region can be reduced. However, first, the steps of the process are complicated, and second, fluorine (F) contained in the silicide penetrates into the gate oxide layer, thereby increasing the threshold voltage. Etc., the electrical characteristics are deteriorated. Third, problems such as short channel effects occur due to difficulty in reducing the depth of the junction region. In addition, in the case of using the titanium silicide, when the width of the gate electrode is reduced to 0.3 μm or less, the size of the titanium silicide crystal becomes larger than the width of the gate electrode, which may cause disconnection due to a poor phase change.
Accordingly, an object of the present invention is to provide a transistor manufacturing method that can solve the above disadvantages by forming a gate electrode in a Y-type using an insulating film spacer.
According to an aspect of the present invention, a pad oxide film and a nitride film are sequentially formed on a silicon substrate on which a field oxide film is formed, and the nitride film and the pad oxide film are sequentially formed to expose the silicon substrate in the channel region. Forming an insulating film spacer on sidewalls of the patterned nitride film and pad oxide film after patterning, forming a gate oxide film on the silicon substrate exposed from the step, and then forming a polysilicon layer on the entire upper surface thereof; Patterning the polysilicon layer from the step to form a gate electrode in the channel region, and then sequentially removing the nitride film and the pad oxide film that are exposed, and bonding the exposed silicon substrate to both sides of the gate electrode from the step. Forming an area, from said step Forming an LDD region in the silicon substrate under both sides of the gate electrode after removing the insulating layer spacer, and forming a silicide layer on the surface of the gate electrode and the junction region from forming the junction region. Characterized in that it further comprises the step. In addition, the junction region is formed by a high concentration of impurity ion implantation and heat treatment, and the ion implantation is characterized in that the high concentration impurity ions are implanted vertically, the low concentration impurity ions are implanted in the LDD region in a gradient ion implantation process The low concentration impurity ions are characterized in that the implanted at an inclination angle of 30 to 70 °.
1A to 1G are cross-sectional views of a device for explaining a transistor manufacturing method according to the present invention.
* Description of the symbols for the main parts of the drawings *
1 silicon substrate 2 field oxide film
3: pad oxide film 4: nitride film
5 insulating film spacer 6 gate oxide film
7: polysilicon layer 7A: gate electrode
8 junction region 9: silicide layer
10: LDD area
Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
1A to 1G are cross-sectional views of a device for explaining a transistor manufacturing method according to the present invention, and FIG. 1A sequentially illustrates a pad oxide film 3 and a nitride film 4 on a silicon substrate 1 on which a field oxide film 2 is formed. The pad oxide film 3 serves to buffer the stress generated by the nitride film 4 from being transferred to the silicon substrate 1 and is formed to a thickness of 50 to 500 kPa. The nitride film 4 is formed to a thickness of 200 to 500 GPa.
FIG. 1B is a cross-sectional view of the nitride film 4 and the pad oxide film 3 sequentially patterned so that the silicon substrate 1 of the channel region CH is exposed, and FIG. 1C shows the patterned nitride film 4 and It is sectional drawing of the state in which the insulating film spacer 5 was formed in the side wall of the pad oxide film 3.
1D is a cross-sectional view of a state in which a polysilicon layer 7 is formed on the entire upper surface after a gate oxide film 6 is formed on the exposed silicon substrate 1 between the insulating film spacers 5. The silicon layer 7 is formed to a thickness of 1000 to 2000 GPa.
FIG. 1E illustrates that the polysilicon layer 7 is patterned to form a gate electrode 7A in the channel region CH, and then the exposed nitride layer 4 and the pad oxide layer 3 are sequentially removed. (7A) A cross sectional view of a state in which a high concentration of impurity ions are injected into an exposed silicon substrate 1 at both sides and heat treated to form a junction region 8, wherein the ion implantation is performed by the impurity ions being introduced into the silicon substrate 1; It should be injected perpendicular to the surface.
1F is a cross-sectional view of the silicide layer 9 formed on the surface of the gate electrode 7A and the junction region 8, and the silicide layer 9 is formed using titanium silicide.
1G shows that the LDD region 10 is formed by removing impurity ions into the silicon substrate 1 under the gate electrode 7A on the lower side of the gate electrode 7A by removing the insulating layer spacer 5 by a wet etching method. As a cross-sectional view of the formed state, the inclined ion implantation step is performed such that the impurity ions are implanted at an inclination angle of 30 to 70 degrees with respect to the surface of the silicon substrate 1. At this time, the concentration distribution of the low concentration impurity ions implanted in the LDD region 10 is lowered from the surface portion of the silicon substrate 1 to effectively suppress the problem caused by the thermoelectric effect.
As described above, according to the present invention, since the gate electrode is formed in the Y-type using the insulating film spacer, the channel length is not reduced, the cross-sectional area of the gate electrode can be effectively increased, and the gate electrode having the polyside structure can be easily formed. Can be. Therefore, the self-resistance value increases due to the decrease of the size of the gate electrode, and the short channel effect and the hot electron effect are prevented. In addition, the transistor manufactured according to the present invention does not generate a junction leakage current because an oxide spacer does not exist on the sidewall of the gate electrode, and thus, the reliability and yield of the device may be improved.

权利要求:
Claims (10)
[1" claim-type="Currently amended] In the transistor manufacturing method,
Sequentially forming a pad oxide film and a nitride film on the silicon substrate on which the field oxide film is formed;
Sequentially patterning the nitride film and the pad oxide film so as to be exposed to the silicon substrate in the channel region from the step, and forming an insulating film spacer on sidewalls of the patterned nitride film and the pad oxide film;
Forming a polysilicon layer on the entire upper surface after forming a gate oxide film on the silicon substrate exposed from the step;
Patterning the polysilicon layer from the step to form a gate electrode in the channel region, and then sequentially removing the nitride film and the pad oxide film exposed;
Forming a junction region in the exposed silicon substrate at both sides of the gate electrode from the step;
Removing the insulating film spacer from the step, and then forming a LDD region of the silicon substrate under the gate electrode.
[2" claim-type="Currently amended] The method of claim 1
And forming a silicide layer on the surface of the gate electrode and the junction region from the forming of the junction region.
[3" claim-type="Currently amended] The method of claim 1,
Wherein the pad oxide film is formed to a thickness of 50 to 500 kV and the nitride film is formed to a thickness of 200 to 500 kV.
[4" claim-type="Currently amended] The method of claim 1,
The polysilicon layer is a transistor manufacturing method, characterized in that formed in a thickness of 1000 to 2000Å.
[5" claim-type="Currently amended] The method of claim 1,
The junction region is formed by high concentration impurity ion implantation and heat treatment.
[6" claim-type="Currently amended] The method of claim 5,
And the ion implantation is performed such that the high concentration of impurity ions are implanted vertically.
[7" claim-type="Currently amended] The method of claim 1,
The silicide layer is a transistor manufacturing method, characterized in that made of titanium silicide.
[8" claim-type="Currently amended] The method of claim 1,
And the insulating film spacers are removed by wet etching.
[9" claim-type="Currently amended] The method of claim 1,
And the low concentration impurity ions are implanted in the LDD region by a gradient ion implantation process.
[10" claim-type="Currently amended] The method of claim 9,
The low concentration impurity ions are implanted at a tilt angle of 30 to 70 °.

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同族专利:

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引用文献:

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公开号 | 申请日 | 公开日 | 申请人 | 专利标题

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法律状态:
1996-12-24|Application filed by 김영환, 현대전자산업 주식회사

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1996-12-24|Priority to KR1019960071502A

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1998-09-25|Publication of KR19980052498A

优先权:

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申请号 | 申请日 | 专利标题

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KR1019960071502A|KR19980052498A|1996-12-24|1996-12-24|Transistor manufacturing method|